`ifndef LILYRISCV_TOP_V
`define LILYRISCV_TOP_V


`include "../core/defines.v"

module LilyRiscv_top(
	input  wire 		  clk	,
	input  wire 		  rstn     		
);

// LilyRiscv to rom 
wire[`InstAddrWidth - 1 : 0] LilyRiscv_inst_addr_o;

//rom to LilyRiscv
wire[`InstWidth - 1 : 0] rom_inst_o;

// open_risc_v to ram
wire       LilyRiscv_mem_wreq_o ;
wire[3:0]  LilyRiscv_mem_wsel_o ;
wire[31:0] LilyRiscv_mem_waddr_o;
wire[31:0] LilyRiscv_mem_wdata_o;
wire 	   LilyRiscv_mem_rreq_o ;
wire[31:0] LilyRiscv_mem_raddr_o;
//ram to open_risc_v
wire[31:0] mem_mem_rdata_i;

LilyRiscv u_LilyRiscv(
	.clk  			(clk  					), 
	.rstn 			(rstn					),
	.inst_i			(rom_inst_o				),
	.inst_addr_o	(LilyRiscv_inst_addr_o	),
	.mem_rreq_o	(LilyRiscv_mem_rreq_o	),
	.mem_raddr_o	(LilyRiscv_mem_raddr_o	),
	.mem_rdata_i	(mem_mem_rdata_i				),
	.mem_wreq_o	(LilyRiscv_mem_wreq_o	),
	.mem_wsel_o	(LilyRiscv_mem_wsel_o	),
	.mem_waddr_o	(LilyRiscv_mem_waddr_o	),
	.mem_wdata_o	(LilyRiscv_mem_wdata_o	)	
);

rom u_rom(
	.clk		(clk),
	.rstn		(rstn),
	.wen		(1'b0),
	.waddr_i	(32'd0),
	.wdata_i	(32'd0),
	.ren		(1'b1),
	.raddr_i	(LilyRiscv_inst_addr_o),
	.rdata_o	(rom_inst_o)
);

mem u_mem(
		.clk  		(clk								),
		.rstn  		(rstn 								),
		.wen  		(LilyRiscv_mem_wsel_o			),//写端口
		.waddr_i	(LilyRiscv_mem_waddr_o			),
		.wdata_i	(LilyRiscv_mem_wdata_o			),
		.ren 		(LilyRiscv_mem_rreq_o			),//读端口	
		.raddr_i	(LilyRiscv_mem_raddr_o			),
		.rdata_o	(mem_mem_rdata_i						)
	);

endmodule


`endif // LILYRISCV_TOP_V